Alex Perotti


Computer engineer with focus on RTL design. Exposure to analog IP RTL development including real number modeling and behavioral modeling. IP RTL lead for tools, flows, and methologies leading to improved RTL quality and improved workflows. Experience with software design and scripting.


Intel Corporation

Hillsboro, OR

SoC RTL Design Engineer

2022 - Present

  • Performing RTL feature development and bug fixes for Intel analog IP used throughout Intel's SoC portfolio across multiple technology nodes
  • Spearheading IP RTL repo development to improve and automate FE design and integration process including tool enablement and enhancement while validating RTL compatibility and ensuring smooth handoff to customers
  • Working closely with analog design and validation engineers to ensure intent, functionality, and specifications are captured in RTL design to fulfill customer needs
  • Leading RTL validation effort for new IP while developing and exercising analog behavior models using real number and UPF modeling
  • SystemVerilog
  • UPF
  • Python
  • Make
  • TCSH

Intel Corporation


RTL Graduate Intern

Summer 2021

  • Redeveloped specific IP functionality from the ground up using SystemVerilog to eliminate corner cases, increase readability, and improve overall modularity for future improvements
  • Created SystemVerilog testbenches utilizing adequate randomization and SVAs to verify functionality of RTL changes before implementing in overall IP repo
  • Implemented broad improvements to existing IP RTL and coded future feature enhancements
  • SystemVerilog
  • SVAs

Samsung Austin Semiconductor

Austin, TX

Engineering Intern

Summer 2019

  • Developed a Windows-based application to aid in the analysis of I-V (current-voltage) test data for semiconductor wafer performance verification
  • Utilized Visual Studio and C# to create a program that queried a database based on user-selected parameters, plotted the requested data, and provided custom tools for analyzing data and exporting data for use with other programs
  • Created Python scripts that prevented semiconductor wafer test tool errors and tool downtime
  • C#
  • Visual Studio
  • Data Processing
  • Python


MS Electrical and Computer Engineering

University of Florida

2020 - 2022

BS in Electrical Engineering

University of Florida

2016 - 2021

photo of me


    • RTL Languages
    • SystemVerilog
    • Verilog
    • VHDL
    • UPF (TCL)
      RTL Tools
    • VCS
    • Xcelium
    • Questa
    • CDC
    • RDC
    • Lint
    • Low Power
    • DFT
      RTL Skills
    • Unix
    • Git
    • RTL Debug
    • SVA Creation
    • Python
    • Make
    • Java
    • C
    • C++
    • C#
    • MATLAB
      ECE Skills
    • Digital Design
    • FPGAs
    • µPs
    • DSP


  • English
  • Spanish


  • Traveling
  • Cooking
  • Board Games